Samsung S5PC110 Manual page 574

S5PC110_UM
1.4.1.5 Memory Direct Command Register (DirectCmd, R/W, Address = 0xF000_0010, 0xF140_0010)
DIRECTCMD
Reserved [31:28]
cmd_type [27:24]
Reserved [23:21]
cmd_chip
cmd_bank [18:16]
cmd_addr [14:0]
Bit
Should be zero.
Type of Direct Command
0x0 = MRS/EMRS (mode register setting),
0x1 = PALL (all banks precharge),
0x2 = PRE (per bank precharge),
0x3 = DPD (deep power down),
0x4 = REFS (self refresh),
0x5 = REFA (auto refresh),
0x6 = CKEL (active/ precharge power down),
0x7 = NOP (exit from active/ precharge power down or deep
power down,
0x8 = REFSX (exit from self refresh)
0x9 = MRR (mode register reading),
0xa ~ 0xf = Reserved
If a direct command is issued, AXI masters must not access
memory. It is strongly recommended to check the command
queue's state by Concontrol.chip0/1_empty before issuing a
direct command
You must disable dynamic power down, dynamic self refresh
and force precharge function (MemControl register).
MRS/EMRS and MRR commands should be issued if all banks
are in idle state.
If MRS/EMRS and MRR is issued to LPDDR2, the CA pins
must be mapped as follows.
MA[7:0] = {cmd_addr[1:0], cmd_bank[2:0], cmd_addr[12:10]},
OP[7:0] = cmd_addr[9:2]
Should be zero.
[20] Chip Number to send the direct command to
0 = Chip 0
1 = Chip 1
Related Bank Address when issuing a direct command
To send a direct command to a chip, additional information
such as the bank address is required.
This register is used in such situations.
Related Address Value when issuing a direct command
To send a direct command to a chip, additional information
such as the address is required.
This register is used in such situations.
Description
1 DRAM CONTROLLER
Initial
R/W
State
0x0
R/W 0x0
0x0
R/W 0x0
R/W 0x0
R/W 0x0
1-31