Samsung S5PC110 Manual page 949

S5PC110_UM
5.8.7.7 Device ALL Endpoints Interrupt Mask Register (DAINTMSK, R/W, Address = 0xEC00_081C)
The Device Endpoint Interrupt Mask register works with the Device Endpoint Interrupt register to interrupt the
application if an event occurs on a device endpoint. However, the Device all Endpoints Interrupt register bit
corresponding to that interrupt remains set.
•
Mask interrupt: 1'b0
•
Unmask interrupt: 1'b1
DAINTMSK Bit
OutEPMsk [31:16]
InEpMsk [15:0]
5.8.7.8 Device VBUS Discharge Time Register (DVBUSDIS, R/W, Address = 0xEC00_0828)
This register specifies the VBUS discharge time after VBUS pulsing during SRP.
DVBUSDIS Bit
Reserved [31:16]
DVBUSDis [15:0]
5.8.7.9 Device VBUS Pulsing Time Register (DVBUSPULSE, R/W, Address = 0xEC00_082C)
This register specifies the VBUS discharge time during SRP.
DVBUSPULSE Bit
Reserved [31:12]
DVBUSPulse [11:0]
OUT EP Interrupt Mask Bits
One bit per OUT endpoint :
Bit 16 for OUT EP 0, bit 31 for OUT EP 15
IN EP Interrupt Mask Bits
One bit per IN endpoint :
Bit 0 for IN EP 0, bit 15 for IN EP 15
-
Device VBUS Discharge Time
Specifies the VBUS discharge time after VBUS pulsing
during SRP.
This value equals :
VBUS discharge time in PHY clocks /1,024
-
Device VBUS Pulsing Time
Specifies the VBUS pulsing time during SRP.
This value equals :
VBUS pulse time in PHY clocks /1,024
Description
Description
Description
5 USB2.0 HS OTG
R/W Initial State
R/W 16'h0
R/W 16'h0
R/W Initial State
- 16'h0
R/W 16'h0B8F
R/W Initial State
- 16'h0
R/W 12'h02C6
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