Samsung S5PC110 Manual page 584

S5PC110_UM
1.4.1.13 AC Timing Register for the Power mode of Memory (TimingPower, R/W, Address = 0xF000_003C,
0xF140_003C)
TIMINGPOWER
Reserved [31:30]
t_faw [29:24]
t_xsr [23:16]
t_xp [15:8]
t_cke
t_mrd
Bit
Should be zero
Four Active Window
t_faw * T(mclk) should be greater than or equal to the
minimum value of memory tFAW
Self refresh exit power down to next valid command delay, in
cycles
t_xsr * T(mclk) should be greater than or equal to the minimum
value of memory tXSR. In case of DDR/DDR2, this value
should be greater than or equal to the minimum value of
memory tXSRD.
Exit power down to next valid command delay, in cycles
t_xp * T(mclk) should be greater than or equal to the minimum
value of memory tXP
[7:4] CKE minimum pulse width (minimum power down mode
duration), in cycles
t_cke should be greater than or equal to the minimum value of
memory tCKE
[3:0] Mode Register Set command period, in cycles
t_mrd should be greater than or equal to the minimum value of
memory tMRD.
Description
1 DRAM CONTROLLER
Initial
R/W
State
0x0
R/W 0xE
R/W 0x1B
R/W 0x4
R/W 0x2
R/W 0x2
1-41