Samsung S5PC110 Manual page 982

S5PC110_UM
7.3 BLOCK DIAGRAM OF SD/ MMC CONTROLLER
INTREQ
System
Bus
(AHB)
HCLK
Domain
SFR
Status
CMD
ARG
Control
AHB slave I/F
DMA
controller
AHB master
Figure 7-1
BaseCLK
Clock Control
Line
Control
FIFO
Control
DPSRAM
SDMMC Clock Domain
7 SD/MMC CONTROLLER
SDCLK
Domain
Status
RSP
CMDRSP
packet
Control
Pad
I/F
Control
Status
DATA
packet
7-2