Pll Control Registers - Samsung S5PC110 Manual

S5PC110_UM
S5PC110 has four internal PLLs, namely, APLL, MPLL, EPLL, and VPLL. The four internal PLLs are controlled by
the following eight special registers:

3.7.2 PLL CONTROL REGISTERS

3.7.2.1 PLL Control Registers (APLL_LOCK / MPLL_LOCK / EPLL_LOCK / VPLL_LOCK)
•
(APLL_LOCK, R/W, Address = 0xE010_0000)
•
(MPLL_LOCK, R/W, Address = 0xE010_0008)
•
(EPLL_LOCK, R/W, Address = 0xE010_0010)
•
(VPLL_LOCK, R/W, Address = 0xE010_0020)
A PLL requires locking period when input frequency is changed or frequency division (multiplication) values are
changed. PLL_LOCK register specifies this locking period, which is based on PLL's source clock. During this
period, output will be masked '0'.
APLL_LOCK /
MPLL_LOCK /
EPLL_LOCK /
VPLL_LOCK
Reserved
PLL_LOCKTIME
Bit
[31:16] Reserved
[15:0] Required period to generate a stable clock output
Description
3 CLOCK CONTROLLER
Initial State
0x0000
0x0FFF
3-18