Samsung S5PC110 Manual page 323

S5PC110_UM
3.7.3.2 Clock Source Control Registers (CLK_SRC1, R/W, Address = 0xE010_0204)
CLK_SRC1
Reserved [31:29]
VPLLSRC_SEL
CSIS_SEL
FIMD_SEL
CAM1_SEL
CAM0_SEL
Reserved
DAC_SEL
Reserved
MIXER_SEL
Reserved
HDMI_SEL
Bit
Reserved
[28] Control MUXVPLLSRC, which is the source clock of VPLL
(0: Oscillator clock, 1: HDMI reference clock)
[27:24] Control MUXCSIS, which is the source clock of CSIS
(0000: XXTI, 0001: XusbXTI, 0010: SCLK_HDMI27M, 0011:
SCLK_USBPHY0, 0100: SCLK_USBPH1, 0101:
SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL, 1000:
SCLKVPLL, OTHERS: reserved)
[23:20] Control MUXFIMD, which is the source clock of FIMD
(0000: XXTI, 0001: XusbXTI, 0010: SCLK_HDMI27M, 0011:
SCLK_USBPHY0, 0100: SCLK_USBPH1, 0101:
SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL, 1000:
SCLKVPLL, OTHERS: reserved)
[19:16] Control MUXCAM1, which is the source clock of CAM0
(0000: XXTI, 0001: XusbXTI, 0010: SCLK_HDMI27M, 0011:
SCLK_USBPHY0, 0100: SCLK_USBPH1, 0101:
SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL, 1000:
SCLKVPLL, OTHERS: reserved)
[15:12] Control MUXCAM0, which is the source clock of CAM0
(0000: XXTI, 0001: XusbXTI, 0010: SCLK_HDMI27M, 0011:
SCLK_USBPHY0, 0100: SCLK_USBPH1, 0101:
SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL, 1000:
SCLKVPLL, OTHERS: reserved)
[11:9] Reserved
[8] Control MUXDAC, which is the source clock of TVENC and
DAC
(0:SCLKVPLL, 1: SCLK_HDMIPHY)
[7:5] Reserved
[4] Control MUXMIXER, which is the source clock of MIXER
(0:SCLK_DAC, 1: SCLK_HDMI)
[3:1] Reserved
[0] Control MUXHDMI, which is the source clock of HDMI link
(0:SCLK_PIXEL, 1: SCLK_HDMIPHY)
Description
3 CLOCK CONTROLLER
Initial State
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
3-26