Samsung S5PC110 Manual page 599

S5PC110_UM
SROM_BW
DataWidth3
ByteEnable2
WaitEnable2
AddrMode2
DataWidth2
ByteEnable1
WaitEnable1
AddrMode1
DataWidth1
ByteEnable0
WaitEnable0
Bit
1 = SROM_ADDR is byte base address
(SROM_ADDR[22:0] <= HADDR[22:0])
Note: When DataWidth3 is "0", SROM_ADDR is byte base
address. (Ignored this bit.)
[12] Data bus width control for Memory Bank3
0 = 8-bit
1 = 16-bit
[11] nWBE / nBE(for UB/LB) control for Memory Bank2
0 = Not using UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0])
1 = Using UB/LB (XrnWBE[1:0] is dedicated nBE[1:0]
[10] Wait enable control for Memory Bank2
0 = Disables WAIT
1 = Enables WAIT
[9] Select SROM ADDR Base for Memory Bank2
0 = SROM_ADDR is Half-word base address.
(SROM_ADDR[22:0] <= HADDR[23:1])
1 = SROM_ADDR is byte base address
(SROM_ADDR[22:0] <= HADDR[22:0])
Note: When DataWidth2 is "0", SROM_ADDR is byte base
address. (Ignored this bit.)
[8] Data bus width control for Memory Bank2
0 = 8-bit
1 = 16-bit
[7] nWBE / nBE(for UB/LB) control for Memory Bank1
0 = Not using UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0])
1 = Using UB/LB (XrnWBE[1:0] is dedicated nBE[1:0]
[6] Wait enable control for Memory Bank1
0 = Disables WAIT
1 = Enables WAIT
[5] Select SROM ADDR Base for Memory Bank1
0 = SROM_ADDR is Half-word base address.
(SROM_ADDR[22:0] <= HADDR[23:1])
1 = SROM_ADDR is byte base address
(SROM_ADDR[22:0] <= HADDR[22:0])
Note: When DataWidth1 is "0", SROM_ADDR is byte base
address. (Ignored this bit.)
[4] Data bus width control for Memory Bank1
0 = 8-bit
1 = 16-bit
[3] nWBE / nBE(for UB/LB) control for Memory Bank0
0 = Not using UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0])
1 = Using UB/LB (XrnWBE[1:0] is dedicated nBE[1:0]
[2] Wait enable control for Memory Bank0
0 = Disables WAIT
Description
2 SROM CONTROLLER
Initial State
0
0
0
0
0
0
0
0
0
1
0
2-7