Ac And Dc Logic Input Levels For Differential Signals; Differential Signals Definition; Differential Swing Requirement For Clock (Ck-Ck) And Strobe (Dqs-Dqs) - Samsung M471B1G73AH0 Hardware User Manual

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10.3 AC and DC Logic Input Levels for Differential Signals

10.3.1 Differential Signals Definition

10.3.2 Differential Swing Requirement for Clock (CK-CK) and Strobe (DQS-DQS)

Symbol
V
differential input high
IHdiff
V
differential input low
ILdiff
V
(AC)
differential input high ac
IHdiff
V
(AC)
differential input low ac
ILdiff
NOTE :
1. Used to define a differential signal slew-rate.
2. for CK - CK use V
/V
(AC) of ADD/CMD and V
IH
IL
then the reduced level applies also here.
3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS need to be within the respective limits (V
nals as well as the limitations for overshoot and undershoot. Refer to "overshoot and Undershoot Specification"
[ Table 3 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS.
Slew Rate [V/ns]
> 4.0
4.0
3.0
2.0
1.8
1.6
1.4
1.2
1.0
< 1.0
datasheet
V
.DIFF.AC.MIN
IH
V
.DIFF.MIN
IH
0.0
V
.DIFF.MAX
IL
V
.DIFF.AC.MAX
IL
Figure 2. Definition of differential ac-swing and "time above ac level" tDVAC
Parameter
2 x (V
; for DQS - DQS use V
REFCA
tDVAC [ps] @ |V
min
75
57
50
38
34
29
22
13
0
0
tDVAC
half cycle
DDR3-800/1066/1333/1600
min
+0.2
NOTE 3
(AC) - V
)
IH
REF
2 x (V
NOTE 3
/V
(AC) of DQs and V
; if a reduced ac-high or ac-low level is used for a signal group,
IH
IL
REFDQ
(AC)| = 350mV
IH/Ldiff
max
-
-
-
-
-
-
-
-
-
-
- 12 -
DDR3 SDRAM
tDVAC
time
unit
max
NOTE 3
V
-0.2
V
NOTE 3
V
(AC) - V
)
V
IL
REF
(DC) max, V
(DC)min) for single-ended sig-
IH
IL
tDVAC [ps] @ |V
(AC)| = 300mV
IH/Ldiff
min
175
170
167
163
162
161
159
155
150
150
Rev. 1.0
NOTE
1
1
2
2
max
-
-
-
-
-
-
-
-
-
-

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