Register Description; Register Map - Samsung S5PC110 Manual

S5PC110_UM

1.4 REGISTER DESCRIPTION

1.4.1 REGISTER MAP

Register
VIC0IRQSTATUS
VIC0FIQSTATUS
VIC0RAWINTR
VIC0INTSELECT
VIC0INTENABLE
VIC0INTENCLEAR
VIC0SOFTINT
VIC0SOFTINTCLEAR
VIC0PROTECTION
VIC0SWPRIORITYMASK
VIC0PRIORITYDAISY
VIC0VECTADDR0
VIC0VECTADDR1
VIC0VECTADDR2
VIC0VECTADDR3
VIC0VECTADDR4
VIC0VECTADDR5
VIC0VECTADDR6
VIC0VECTADDR7
VIC0VECTADDR8
VIC0VECTADDR9
VIC0VECTADDR10
VIC0VECTADDR11
VIC0VECTADDR12
VIC0VECTADDR13
VIC0VECTADDR14
VIC0VECTADDR15
VIC0VECTADDR16
VIC0VECTADDR17
VIC0VECTADDR18
Address R/W
0xF200_0000 R
0xF200_0004 R
0xF200_0008 R
0xF200_000C R/W
0xF200_0010 R/W
0xF200_0014 W
0xF200_0018 R/W
0xF200_001C W
0xF200_0020 R/W
0xF200_0024 R/W
0xF200_0028 R/W
0xF200_0100 R/W
0xF200_0104 R/W
0xF200_0108 R/W
0xF200_010C R/W
0xF200_0110 R/W
0xF200_0114 R/W
0xF200_0118 R/W
0xF200_011C R/W
0xF200_0120 R/W
0xF200_0124 R/W
0xF200_0128 R/W
0xF200_012C R/W
0xF200_0130 R/W
0xF200_0134 R/W
0xF200_0138 R/W
0xF200_013C R/W
0xF200_0140 R/W
0xF200_0144 R/W
0xF200_0148 R/W
1 VECTORED INTERRUPT CONTROLLER
Description
Specifies the IRQ Status Register
Specifies the FIQ Status Register
Specifies the Raw Interrupt Status
Register
Specifies the Interrupt Select Register
Specifies the Interrupt Enable Register
Specifies the Interrupt Enable Clear
Register
Specifies the Software Interrupt Register
Specifies the Software Interrupt Clear
Register
Specifies the Protection Enable Register
Software Priority Mask Register
Specifies the Vector Priority Register for
Daisy Chain
Specifies the Vector Address 0 Register
Specifies the Vector Address 1 Register
Specifies the Vector Address 2 Register
Specifies the Vector Address 3 Register
Specifies the Vector Address 4 Register
Specifies the Vector Address 5 Register
Specifies the Vector Address 6 Register
Specifies the Vector Address 7 Register
Specifies the Vector Address 8 Register
Specifies the Vector Address 9 Register
Specifies the Vector Address 10 Register
Specifies the Vector Address 11 Register
Specifies the Vector Address 12 Register
Specifies the Vector Address 13 Register
Specifies the Vector Address 14 Register
Specifies the Vector Address 15 Register
Specifies the Vector Address 16 Register
Specifies the Vector Address 17 Register
Specifies the Vector Address 18 Register
Reset Value
0x00000000
0x00000000
-
0x00000000
0x00000000
-
0x00000000
-
0x0
0xFFFF
0xF
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
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