Samsung S5PC110 Manual page 582

S5PC110_UM
1.4.1.10 AC Timing Register for Auto Refresh of memory (TimingAref, R/W, Address = 0xF000_0030,
0xF140_0030)
TIMINGAREF
Reserved [31:16]
t_refi [15:0]
1.4.1.11 AC Timing Register for the Row of memory (TimingRow, R/W, Address = 0xF000_0034,
0xF140_0034)
TIMINGROW
t_rfc [31:24]
t_rrd [23:20]
t_rp [19:16]
t_rcd [15:12]
t_rc [11:6]
t_ras
Bit
Should be zero
Average Periodic Refresh Interval
Should be minimum memory tREFI (all bank) < t_refi * T(mclk),
For example, for the all bank refresh period of 7.8us, and an
mclk frequency of 133MHz, the following value should be
programmed :
Bit
Auto refresh to Active / Auto refresh command period, in
cycles
t_rfc * T(mclk) should be greater than or equal to the minimum
value of memory tRFC.
Active bank A to Active bank B delay, in cycles
t_rrd * T(mclk) should be greater than or equal to the minimum
value of memory tRRD.
Precharge command period, in cycles
t_rp * T(mclk) should be greater than or equal to the minimum
value of memory tRP.
Active to Read or Write delay, in cycles
t_rcd * T(mclk) should be greater than or equal to the minimum
value of memory tRCD
Active to Active period, in cycles
t_rc * T(mclk) should be greater than or equal to the minimum
value of memory tRC.
[5:0] Active to Precharge command period, in cycles
t_ras * T(mclk) should be greater than or equal to the minimum
value of memory tRAS.
Description
7.8 us * 133 MHz = 1038
Description
1 DRAM CONTROLLER
Initial
R/W
State
0x0
R/W 0x40E
Initial
R/W
State
R/W 0xF
R/W 0x2
R/W 0x3
R/W 0x3
R/W 0xA
R/W 0x6
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