Samsung S5PC110 Manual page 46

S5PC110_UM
Pin Name GPIO
XpwmTOUT[3] GPD0[3]
Xi2c0SDA GPD1[0]
Xi2c0SCL GPD1[1]
Xi2c1SDA GPD1[2]
Xi2c1SCL GPD1[3]
Xi2c2SDA GPD1[4]
Xi2c2SCL GPD1[5]
XciPCLK GPE0[0]
XciVSYNC GPE0[1]
XciHREF GPE0[2]
XciDATA[0] GPE0[3]
XciDATA[1] GPE0[4]
XciDATA[2] GPE0[5]
XciDATA[3] GPE0[6]
XciDATA[4] GPE0[7]
XciDATA[5] GPE1[0]
XciDATA[6] GPE1[1]
XciDATA[7] GPE1[2]
XciCLKenb GPE1[3]
XciFIELD GPE1[4]
XvHSYNC GPF0[0]
XvVSYNC GPF0[1]
XvVDEN GPF0[2]
XvVCLK GPF0[3]
XvVD[0] GPF0[4]
XvVD[1] GPF0[5]
XvVD[2] GPF0[6]
XvVD[3] GPF0[7]
XvVD[4] GPF1[0]
XvVD[5] GPF1[1]
XvVD[6] GPF1[2]
XvVD[7] GPF1[3]
XvVD[8] GPF1[4]
XvVD[9] GPF1[5]
XvVD[10] GPF1[6]
XvVD[11] GPF1[7]
Func0 Func1
TOUT_3
I2C0_SDA
I2C0_SCL
I2C1_SDA
I2C1_SCL
I2C2_SDA IEM_SCLK
I2C2_SCL IEM_SPWI
CAM_A_PCLK
CAM_A_VSYNC
CAM_A_HREF
CAM_A_DATA[0]
CAM_A_DATA[1]
CAM_A_DATA[2]
CAM_A_DATA[3]
CAM_A_DATA[4]
CAM_A_DATA[5]
CAM_A_DATA[6]
CAM_A_DATA[7]
CAM_A_CLKOUT
CAM_A_FIELD
LCD_HSYNC SYS_CS0
LCD_VSYNC SYS_CS1
LCD_VDEN SYS_RS
LCD_VCLK SYS_WE
LCD_VD[0] SYS_VD[0]
LCD_VD[1] SYS_VD[1]
LCD_VD[2] SYS_VD[2]
LCD_VD[3] SYS_VD[3]
LCD_VD[4] SYS_VD[4]
LCD_VD[5] SYS_VD[5]
LCD_VD[6] SYS_VD[6]
LCD_VD[7] SYS_VD[7]
LCD_VD[8] SYS_VD[8]
LCD_VD[9] SYS_VD[9]
LCD_VD[10] SYS_VD[10]
LCD_VD[11] SYS_VD[11]
Func2 Func3
VEN_HSYNC
VEN_VSYNC
VEN_HREF
V601_CLK
VEN_DATA[0]
VEN_DATA[1]
VEN_DATA[2]
VEN_DATA[3]
VEN_DATA[4]
VEN_DATA[5]
VEN_DATA[6]
VEN_DATA[7]
V656_DATA[0]
V656_DATA[1]
V656_DATA[2]
V656_DATA[3]
2 GENERAL PURPOSE INPUT/ OUTPUT
@Reset Sleep
Default
PUD I/O State
GPI PD I(L)
GPI PD I(L)
GPI PD I(L)
GPI PD I(L)
GPI PD I(L)
GPI PD I(L)
GPI PD I(L)
GPI PD I(L)
GPI PD I(L)
GPI PD I(L)
GPI PD I(L)
GPI PD I(L)
GPI PD I(L)
GPI PD I(L)
GPI PD I(L)
GPI PD I(L)
GPI PD I(L)
GPI PD I(L)
GPI PD I(L)
GPI PD I(L)
GPI PD I(L)
GPI PD I(L)
GPI PD I(L)
GPI PD I(L)
GPI PD I(L)
GPI PD I(L)
GPI PD I(L)
GPI PD I(L)
GPI PD I(L)
GPI PD I(L)
GPI PD I(L)
GPI PD I(L)
GPI PD I(L)
GPI PD I(L)
GPI PD I(L)
GPI PD I(L)
Pad Type
A1 PBIDIRSE_G
A1 PBIDIRSE_G
A1 PBIDIRSE_G
A1 PBIDIRSE_G
A1 PBIDIRSE_G
A1 PBIDIRSE_G
A1 PBIDIRSE_G
A1 PBIDIRSE_G
A1 PBIDIRSE_G
A1 PBIDIRSE_G
A1 PBIDIRSE_G
A1 PBIDIRSE_G
A1 PBIDIRSE_G
A1 PBIDIRSE_G
A1 PBIDIRSE_G
A1 PBIDIRSE_G
A1 PBIDIRSE_G
A1 PBIDIRSE_G
A1 PBIDIRSE_G
A1 PBIDIRSE_G
A1 PBIDIRSE_G
A1 PBIDIRSE_G
A1 PBIDIRSE_G
A1 PBIDIRSE_G
A1 PBIDIRSE_G
A1 PBIDIRSE_G
A1 PBIDIRSE_G
A1 PBIDIRSE_G
A1 PBIDIRSE_G
A1 PBIDIRSE_G
A1 PBIDIRSE_G
A1 PBIDIRSE_G
A1 PBIDIRSE_G
A1 PBIDIRSE_G
A1 PBIDIRSE_G
A1 PBIDIRSE_G
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