Samsung S5PC110 Manual page 589

S5PC110_UM
1.4.1.20 PHY Test Register 1 (PhyTest1, R, Address = 0xF000_005C, 0xF140_005C)
PHYTEST1
ctrl_fb_cnt3 [31:24]
ctrl_fb_cnt2 [23:16]
ctrl_fb_cnt1 [15:8]
ctrl_fb_cnt0
1.4.1.21 Quality of Service Control Register n (QosControl n, R/W, Address = 0xF000_0060 + 8n (n=0~15,
integer), 0xF140_0060 + 8n (n=0~15, integer)
QOSCONTROLn
Reserved [31:28]
qos_cnt [27:16]
qos_cnt_f
Reserved
qos_en
NOTE: If qos fast is enabled, the QoSControl(n) of 4,5,6,7,8,9,10,11,13,14 & 15 are dedicated to each specific IP that is refer
to .
Table 1-1
Bit
Count value for data3 channel
Count value for data2 channel
Count value for data1 channels
[7:0] Count value for data0 channel
Bit
Should be zero
QoS Cycles
0xn = n aclk cycles
The matched ARID/AWID uses this value for its timeout
counters instead of ConControl.timeout_cnt.
[15:4]
QoS cycles for fast request
0xn = n aclk cycles
When Concontrol.qos_fast_en is enabled and input pin
qos_fast[n] bit is 1, this qos_cnt_f value is loaded to the
timeout counter.
[3:1] Should be zero
[0] QoS Enable
0x0 = Disable
0x1 = Enable
If this function is enabled, its timeout counter works and the
ARID/AWID is masked with QoSConfig.qos_mask and
compared with QoSConfig.qos_id
Description
Description
1 DRAM CONTROLLER
Initial
R/W
State
R 0x0
R 0x0
R 0x0
R 0x0
Initial
R/W
State
0x0
R/W 0x0
R/W 0x0
0x0
R/W 0x0
1-46