Samsung S5PC110 Manual page 662

S5PC110_UM
4.5.2.8 Only Word Access is Allowed Spare Area ECC Register (NFSECCD, R/W, Address = 0xB0E0_001C)
NFSECCD
Reserved [31:24]
SECCData1 [23:16]
Reserved
SECCData0
NOTE: Only word access is allowed.
4.5.2.9 Programmable Start Block Address Register (NFSBLK, R/W, Address = 0xB0E0_0020)
NFSBLK
Reserved [31:24]
SBLK_ADDR2 [23:16]
SBLK_ADDR1
SBLK_ADDR0
NOTE: Advance Flash's block Address start from 3-address cycle. So block address register only needs 3-bytes. For more
information about lock scheme, refer to the 4.3.12 .
4.5.2.10 Programmable End Block Address Register (NFEBLK, R/W, Address = 0xB0E0_0024)
NFEBLK
Reserved [31:24]
EBLK_ADDR2 [23:16]
EBLK_ADDR1 [15:8]
EBLK_ADDR0 [7:0]
NOTE: Advance Flash's block Address start from 3-address cycle. So block address register only needs 3-bytes.
For more information about lock scheme, refer to the 4.3.12 .
Bit
Reserved
nd
2 ECC
Note: In software mode, read this register when you need to
nd
read 2 ECC value from NAND Flash memory
[15:8] Reserved
st
[7:0]
1 ECC
Note: In software mode, read this register when you need to
st
read 1 ECC value from NAND Flash memory. This register
has the same read function as NFDATA.
Bit
Reserved
rd
The 3 block address of the block erase operation
nd
[15:8]
The 2 block address of the block erase operation
st
[7:0]
The 1 block address of the block erase operation
(Only bit [7:5] are valid)
Bit
Reserved
rd
The 3 block address of the block erase operation
nd
The 2 block address of the block erase operation
st
The 1 block address of the block erase operation
(Only bit [7:5] are valid)
Description
Description
Description
4 NAND FLASH CONTROLLER
Initial State
0x00
0xFF
0x00
0xFF
Initial State
0x00
0x00
0x00
0x00
Initial State
0x00
0x00
0x00
0x00
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