Samsung S5PC110 Manual page 351

S5PC110_UM
3.7.7.2 Clock Divider Status SFRs (CLK_DIV_STAT1, R, Address = 0xE010_1004)
CLK_DIV_STAT1
Reserved
DIV_G2D
Reserved
DIV_DPM
DIV_DVSEM
DIV_DMC0
DIV_PWI
DIV_HPM
DIV_COPY
DIV_ONENAND
DIV_AUDIO2
DIV_AUDIO1
DIV_AUDIO0
Reserved
DIV_PWM
Reserved
DIV_SPI1
DIV_SPI0
Bit
[31:21] Reserved
[20] DIVG2D status (0: stable, 1: divider is changing)
[19:18] Reserved
[17] DIVDPM status (0: stable, 1: divider is changing)
[16] DIVDVSEM status (0: stable, 1: divider is changing)
[15] DIVDMC0 status (0: stable, 1: divider is changing)
[14] DIVPWI status (0: stable, 1: divider is changing)
[13] DIVHPM status (0: stable, 1: divider is changing)
[12] DIVCOPY status (0: stable, 1: divider is changing)
[11] DIVFLASH status (0: stable, 1: divider is changing)
[10] DIVAUDIO2 status (0: stable, 1: divider is changing)
[9] DIVAUDIO1 status (0: stable, 1: divider is changing)
[8] DIVAUDIO0 status (0: stable, 1: divider is changing)
[7:4] Reserved
[3] DIVPWM status (0: stable, 1: divider is changing)
[2] Reserved
[1] DIVSPI1 status (0: stable, 1: divider is changing)
[0] DIVSPI0 status (0: stable, 1: divider is changing)
Description
3 CLOCK CONTROLLER
Initial State
0x0
0
0x0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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