S5PC110_UM
2.2.14.2 Port Group GPF3 Control Register (GPF3DAT, R/W, Address = 0xE020_0184)
GPF3DAT
GPF3DAT[5:0]
2.2.14.3 Port Group GPF3 Control Register (GPF3PUD, R/W, Address = 0xE020_0188)
GPF3PUD
GPF3PUD[n]
2.2.14.4 Port Group GPF3 Control Register (GPF3DRV, R/W, Address = 0xE020_018C)
GPF3DRV
GPF3DRV[n]
2.2.14.5 Port Group GPF3 Control Register (GPF3CONPDN, R/W, Address = 0xE020_0190)
GPF3CONPDN
GPF3[n]
2.2.14.6 Port Group GPF3 Control Register (GPF3PUDPDN, R/W, Address = 0xE020_0194)
GPF3PUDPDN
GPF3[n]
Bit
[5:0]
When the port is configured as input port, the corresponding
bit is the pin state. When the port is configured as output
port, the pin state is the same as the corresponding bit.
When the port is configured as functional pin, the undefined
value will be read.
Bit
[2n+1:2n]
00 = Pull-up/ down disabled
01 = Pull-down enabled
n=0~5
10 = Pull-up enabled
11 = Reserved
Bit
[2n+1:2n]
00 = 1x
10 = 2x
n=0~5
01 = 3x
11 = 4x
Bit
[2n+1:2n]
00 = Output 0
01 = Output 1
n=0~5
10 = Input
11 = Previous state
Bit
[2n+1:2n]
00 = Pull-up/ down disabled
01 = Pull-down enabled
n=0~5
10 = Pull-up enabled
11 = Reserved
2 GENERAL PURPOSE INPUT/ OUTPUT
Description
Description
Description
Description
Description
Initial State
0x00
Initial State
0x0555
Initial State
0x0000
Initial State
0x00
Initial State
0x00
2-71