Samsung S5PC110 Manual page 329

S5PC110_UM
3.7.3.8 Clock Source Control Registers (CLK_SRC_MASK0, R/W, Address = 0xE010_0280)
CLK_SRC_MASK0
Reserved
PWI_MASK
Reserved
SPDIF_MASK
AUDIO2_MASK
AUDIO1_MASK
AUDIO0_MASK
Reserved
PWM_MASK
Reserved
SPI1_MASK
SPI0_MASK
UART3_MASK
UART2_MASK
UART1_MASK
UART0_MASK
MMC3_MASK
MMC2_MASK
MMC1_MASK
MMC0_MASK
FINVPLL_MASK
CSIS_MASK
FIMD_MASK
CAM1_MASK
CAM0_MASK
DAC_MASK
MIXER_MASK
HDMI_MASK
Bit
[31:30] Reserved
[29] Mask output clock of MUXPWI (0: disable, 1: enable)
[28] Reserved
[27] Mask output clock of MUXSPDIF (0: disable, 1: enable)
[26] Mask output clock of MUXAUDIO2 (0: disable, 1: enable)
[25] Mask output clock of MUXAUDIO1 (0: disable, 1: enable)
[24] Mask output clock of MUXAUDIO0 (0: disable, 1: enable)
[23:20] Reserved
[19] Mask output clock of MUXPWM (0: disable, 1: enable)
[18] Reserved
[17] Mask output clock of MUXSPI1 (0: disable, 1: enable)
[16] Mask output clock of MUXSPI0 (0: disable, 1: enable)
[15] Mask output clock of MUXUART3 (0: disable, 1: enable)
[14] Mask output clock of MUXUART2 (0: disable, 1: enable)
[13] Mask output clock of MUXUART1 (0: disable, 1: enable)
[12] Mask output clock of MUXUART0 (0: disable, 1: enable)
[11] Mask output clock of MUXMMC3 (0: disable, 1: enable)
[10] Mask output clock of MUXMMC2 (0: disable, 1: enable)
[9] Mask output clock of MUXMMC1 (0: disable, 1: enable)
[8] Mask output clock of MUXMMC0 (0: disable, 1: enable)
[7] Mask output clock of MUXVPLLSRC (0: disable, 1: enable)
[6] Mask output clock of MUXCSIS (0: disable, 1: enable)
[5] Mask output clock of MUXFIMD (0: disable, 1: enable)
[4] Mask output clock of MUXCAM1 (0: disable, 1: enable)
[3] Mask output clock of MUXCAM0 (0: disable, 1: enable)
[2] Mask output clock of MUXDAC (0: disable, 1: enable)
[1] Mask output clock of MUXMIXER (0: disable, 1: enable)
[0] Mask output clock of MUXHDMI (0: disable, 1: enable)
Description
3 CLOCK CONTROLLER
Initial State
0x3
1
1
1
1
1
1
0xF
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
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