Samsung S5PC110 Manual page 858

S5PC110_UM
3.4.2.2 Clock Configuration Register
•
CLK_CFG0, R/W, Address = 0xE130_0004
•
CLK_CFG1, R/W, Address = 0xE140_0004
CLK_CFGn
SPI_CLKSEL
ENCLK
SPI_SCALER
Bit
[9] Clock source selection to generate SPI clock-out
0 = PCLK
1 = SPI_EXT_CLK
[8] Clock enable/ disable
0 = Disable
1 = Enable
[7:0] SPI clock-out division rate
SPI clock-out = Clock source / (2 x (Prescaler value +1))
3 SERIAL PERIPHERAL INTERFACE
Description Initial State
0
0
0
3-10