Samsung S5PC110 Manual page 659

S5PC110_UM
4.5.2.2 Control Register (NFCONT, R/W, Address = 0xB0E0_0004)
NFCONT
Reserved
Reg_nCE3
Reg_nCE2
Reserved
MLCEccDirection
LockTight
LOCK
Reserved
EnbMLCEncInt
EnbMLCDecInt
EnbIllegalAccINT
EnbRnBINT
RnB_TransMode
Bit
[31:24] Reserved
[23] NAND Flash Memory nRCS[3] signal control
0 = Force nRCS[3] to low (Enable chip select)
1 = Force nRCS[3] to High (Disable chip select)
[22] NAND Flash Memory nRCS[2] signal control
0 = Force nRCS[2] to low (Enable chip select)
1 = Force nRCS[2] to High (Disable chip select)
[21:19] Reserved
[18] 4-bit, ECC encoding / decoding control
0 = Decoding 4-bit ECC, It is used for page read
1 = Encoding 4-bit ECC, It is be used for page program
[17] Lock-tight configuration
0 = Disable lock-tight
1 = Enable lock-tight,
If this bit is set to 1, you cannot clear this bit.
For more information, refer to the
data protection".
[16] Soft Lock configuration
0 = Disable lock
1 = Enable lock
Software can modify soft lock area any time.
For more information, refer to the
[15:14] Reserved
[13] 4-bit ECC encoding completion interrupt control
0 = Disable interrupt
1 = Enable interrupt
[12] 4-bit ECC decoding completion interrupt control
0 = Disable interrupt
1 = Enable interrupt
[11] Reserved
[10] Illegal access interrupt control
0 = Disable interrupt
1 = Enable interrupt
Illegal access interrupt occurs when CPU tries to program or
erase locking area (the area setting in NFSBLK
(0xB0E0_0020) to NFEBLK (0xB0E0_0024)-1.
[9] RnB status input signal transition interrupt control
0 = Disable RnB interrupt
1 = Enable RnB interrupt
[8] RnB transition detection configuration
0 = Detect rising edge
1 = Detect falling edge
Description
4.3.12 "Lock scheme for
4.3.12 ".
4 NAND FLASH CONTROLLER
Initial State
0
1
1
0
0
0
1
00
0
0
0
0
0
0
4-18