Samsung S5PC110 Manual page 636

S5PC110_UM
3.8.3.7 DMA Transfer Status Register (A_TRANS_STATUS, R, Address = 0xB060_041C)
A_TRANS_
Bit
STATUS
- [31:19]
TD [18]
TB [17]
TE [16]
- [15:0]
Reserved
Transfer Done
This status is used to check whether the DMA transfer is complete
or not. After the DMA transfer is successfully completed, TD bit is
set to 1.
Transfer Busy
This status is used to check whether the DMA transfer is in
progress or not
Transfer Error
This status is used to check whether there has been an error
during the DMA transfer. There are three error sources in the DMA
engine.
First error source is the response signal (HRESP) from the slave
on the AHB. As soon as the DMA engine receives any ERROR
response from the slave on the AHB during the DMA transfer, TE
bit is set to 1 and the DMA operation stops.
Second error sources are the incorrect source/ destination address
and transfer direction configurations. The DMA engine has two
AHB master ports and these are connected to the external AHB
and the internal AHB, respectively. Therefore source and
destination address registers cannot be configured to the slaves on
the same AHB for the DMA operation. Due to this fact, only
following two cases are allowed for source/ destination address
register value: 1) source memory is the slave on the external AHB
and destination memory is the slave on the internal AHB, 2) source
memory is the slave on the internal AHB and destination memory is
the slave on the external AHB. If source/ destination address
registers are not configured to satisfy this condition, the DMA
engine does not perform any data transfer and TE bit is set to 1.
Also, if the transfer direction register is not configured correctly
according to source/ destination addresses, the DMA engine does
not perform any data transfer and TE bit is set to 1.
Third error source is the incorrect source/ destination burst length
or data width configurations. If any of these four fields (SBL, DBL,
SDW, DDW) is configured with reserved value, the DMA engine
does not perform any data transfer and TE bit is set to 1.
Reserved
Description
3 ONENAND CONTROLLER
Initial State
-
0b
0b
0b
0000h
3-34