Samsung S5PC110 Manual page 633

S5PC110_UM
DMA_SRC_CFG
3.8.3.3 DMA Destination Address Register (DMA_DST_ADDR, R/W, Address = 0xB060_0408)
DMA_DST_ADDR
DA
Bit
memory address should be the multiple of the HSIZE (data
width). If this address alignment condition is not satisfied, the
actual data width on the AHB during the DMA transfer will be
smaller than the access size specified in these bits.
00b = 8-bit (byte)
01b = 16-bit (half word)
10b = 32-bit (word)
11b = Reserved
Bit
[31:0]
Destination Address
Destination address on the AHB for the DMA operation. This
address is the start address to which the DMA engine performs
write operation.
Description
Description
3 ONENAND CONTROLLER
Initial State
Initial State
00000000h
3-31