Samsung S5PC110 Manual page 316

S5PC110_UM
PLL_CON register controls the operation of each PLL. If ENABLE bit is set, the corresponding PLL generates
output after PLL locking period. The MDIV, PDIV, and SDIV values control the output frequency of PLL. The PLL
also generates the output frequency when MDIV, PDIV, and VSEL are changed. However, the PLL locking period
is not applied if only SDIV is changed. PLL Control Registers (APLL_CON0/APLL_CON1, R/W, Address =
0xE010_0100/0xE010_0104)
APLL_CON0
ENABLE
Reserved
LOCKED
Reserved
MDIV
Reserved
PDIV
Reserved
SDIV
The reset value of APLL_CON0 generates 800 MHz output clock, if the input clock frequency is 24 MHz.
Equation to calculate the output frequency:
FOUT = MDIV X FIN / (PDIV × 2
where, MDIV, PDIV, SDIV for APLL and MPLL must meet the following conditions :
PDIV: 1 ≤ PDIV ≤ 63
MDIV: 64 ≤ MDIV ≤ 1023
SDIV: 1 ≤ SDIV ≤ 5
Fref (=FIN / PDIV): 1MHz ≤ Fref ≤ 12MHz
FVCO (=2 × MDIV × FIN / PDIV): 1000MHz ≤ FVCO ≤ 2060MHz
Refer to
3.3.1 Recommended PLL PMS Value for APLL
APLL should be turned on before entering following low-power modes. Deep idle, stop, deep stop,
Caution:
sleep mode. APLL will be automatically turned off while entering those low-power modes.
Bit
[31] PLL enable control (0: disable, 1: enable)
[30] Reserved
[29] PLL locking indication
0 = Unlocked
1 = Locked
Read Only
[28:26] Reserved
[25:16] PLL M divide value
[15:14] Reserved
[13:8] PLL P divide value
[7:3] Reserved
[2:0] PLL S divide value
SDIV-1
)
Description
for recommended PMS values.
3 CLOCK CONTROLLER
Initial State
0
0
0
0x0
0xC8
0
0x3
0
0x1
3-19