Samsung S5PC110 Manual page 824

S5PC110_UM
1.6.1.6 UART Error Status Register
•
UERSTAT0, R, Address = 0xE290_0014
•
UERSTAT1, R, Address = 0xE290_0414
•
UERSTAT2, R, Address = 0xE290_0814
•
UERSTAT3, R, Address = 0xE290_0C14
There are four UART Rx error status registers in the UART block, namely, UERSTAT0, UERSTAT1, UERSTAT2
and UERSTAT3.
UERSTATn
Reserved [31:4] Reserved
Break Detect
Frame Error
Parity Error
Overrun Error
NOTE: These bits (UERSATn[3:0]) are automatically cleared to 0 if UART error status register is read
Bit
[3] This bit is automatically set to 1 to indicate that a break signal has
been received.
0 = No break signal is received
1 = Break signal is received (Interrupt is requested.)
[2] This bit is automatically set to 1 if a frame error occurs during the
receive operation.
0 = No frame error occurs during the receive operation
1 = Frame error occurs (Interrupt is requested.) during the receive
operation
[1] This bit is automatically set to 1 if a parity error occurs during the
receive operation.
0 = No parity error occurs during receive the receive operation
1 = Parity error occurs (Interrupt is requested.) the receive
operation
[0] This bit is automatically set to 1 automatically if an overrun error
occurs during the receive operation.
0 = No overrun error occurs during the receive operation
1 = Overrun error occurs (Interrupt is requested.) during the
receive operation
1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER
Description Initial State
0
0
0
0
0
1-22