Samsung S5PC110 Manual page 541

Figure
Number
Figure 1-1 Overall Block Diagram ...................................................................................................................... 1-2
Figure 1-2 Linear Address Mapping................................................................................................................... 1-7
Figure 1-3 Interleaved Address Mapping ........................................................................................................... 1-8
Figure 1-4 Timing Diagram of Timeout Precharge........................................................................................... 1-10
Figure 1-5 Adaptive DRAM QoS Scheme Configuration ................................................................................. 1-12
Figure 1-6 Timing Diagram of Read Data Capture (DDR2, zero delay, RL=3, rd_fetch=1) ............................ 1-14
Figure 1-7 Timing Diagram of Read Data Capture (DDR2, non-zero delay, RL=3, rd_fetch=2) ..................... 1-15
Figure 1-8 Timing Diagram of Read Data Capture (LPDDR/LPDDR2, zero delay, RL=3, rd_fetch=1)........ 1-16
Figure 1-9 Timing Diagram of Read Data Capture (LPDDR/LPDDR2, non-zero delay, RL=3, rd_fetch=2). 1-17
Figure 1-10 Timing Diagram of Read Data Capture
Figure 1-11 DLL Lock Procedure....................................................................................................................... 1-34
Figure 1-12 Board Level Connection Diagram for DQS Cleaning ..................................................................... 1-36
Figure 1-13 DQS Cleaning for LPDDR if tAC Min ............................................................................................. 1-37
Figure 1-14 DQS Cleaning for LPDDR if tAC Max ............................................................................................ 1-37
Figure 1-15 DQS cleaning for DDR2 ................................................................................................................. 1-38
Figure 2-1 Block Diagram of SROM Controller .................................................................................................. 2-1
Figure 2-2 SROM Controller nWAIT Timing Diagram........................................................................................ 2-2
Figure 2-3 SROM Controller Read Timing Diagram .......................................................................................... 2-3
Figure 2-4 SROM Controller Write Timing Diagram .......................................................................................... 2-3
Figure 3-1 OneNAND Controller Block Diagram (A: AHB Slave Port, B: AHB Master Port, and C: OneNAND
Interface Port) ......................................................................................................................................................... 3-3
Figure 3-2 OneNAND Accesses (OneNAND Controller Address: 0xB0000000 ~ 0xB01FFFFF)
External AHB Master (ARM Processor) ................................................................................................................. 3-9
Figure 3-3 Control Register Accesses (OneNAND Controller Address: 0xB0600000 ~ 0xB07FFFFF) by the
External AHB Master (ARM Processor) ............................................................................................................... 3-10
ONENAND_IF_CTRL (OneNAND Interface Control) Register Update Flow ................................. 3-13
Figure 3-4
Figure 3-5 ONENAND_IF_ASYNC_TIMING_CTRL (OneNAND Interface Async Timing Control) Register
Update Flow 3-14
Figure 3-6 OneNAND Device INT Pin Rising Edge Wait Operations with a Polling Method........................... 3-16
Figure 3-7 OneNAND Device INT Pin Rising Edge Wait Operations with an Interrupt-Driven Method ........ 3-16
Figure 3-8 OneNAND Device INT Pin Rising Edge Wait Operation Timing Diagram DMA Engin .................. 3-17
Figure 3-9 Data Transfer between OneNAND and External Memory by the Internal DMA Engine (OneNAND
Read/ Write) 3-18
Figure 3-10 Internal DMA Engine Operations with a Polling Method ................................................................ 3-19
Figure 3-11 Internal DMA Engine Operations with an Interrupt-Driven Method ................................................ 3-20
Figure 3-12 ONENAND Interface Synchronous Read Timing ........................................................................... 3-25
Figure 3-13 OneNAND Interface Synchronous Write Timing ............................................................................ 3-25
Figure 3-14 OneNAND Interface Asynchronous Read Timing .......................................................................... 3-28
Figure 3-15 OneNAND Interface Asynchronous Write Timing .......................................................................... 3-28
Figure 4-1 NAND Flash Controller Block Diagram............................................................................................. 4-2
Figure 4-2 CLE and ALE Timing (TACLS=1, TWRPH0=0, TWRPH1=0) .......................................................... 4-2
Figure 4-3 nWE and nRE Timing (TWRPH0=0, TWRPH1=0) ........................................................................... 4-3
List of Figures
Title
(LPDDR/LPDDR2, low frequency, RL=3, rd_fetch=0) 1-18
Page
Number
by the