Samsung S5PC110 Manual page 861

S5PC110_UM
3.4.2.5 SPI Interrupt Enable Register
•
SPI_INT_EN0, R/W, Address = 0xE130_0010
•
SPI_INT_EN1, R/W, Address = 0xE140_0010
SPI_INT_ENn
INT_EN_TRAILING
INT_EN_RX_OVERRUN
INT_EN_RX_UNDERRUN
INT_EN_TX_OVERRUN
INT_EN_TX_UNDERRUN
INT_EN_RX_FIFO_RDY
INT_EN_TX_FIFO_RDY
Bit
[6] Interrupt Enable for trailing count to be 0
0 = Disables
1 = Enables
[5] Interrupt Enable for RxOverrun
0 = Disables
1 = Enables
[4] Interrupt Enable for RxUnderrun
0 = Disables
1 = Enables
[3] Interrupt Enable for TxOverrun
0 = Disables
1 = Enables
[2] Interrupt Enable for TxUnderrun. In slave mode, this bit
must be clear first after turning on slave TX path.
0 = Disables
1 = Enables
[1] Interrupt Enable for RxFifoRdy (INT mode)
0 = Disables
1 = Enables
[0] Interrupt Enable for TxFifoRdy (INT mode)
0 = Disables
1 =Enables
3 SERIAL PERIPHERAL INTERFACE
Description Initial State
0
0
0
0
0
0
0
3-13