Samsung S5PC110 Manual page 797

4.3.1 Register Map .................................................................................................................................... 4-4
4.3.2 Implemented Specific Registers ....................................................................................................... 4-6
5 USB2.0 HS OTG ..........................................................................................5-1
5.1 Overview of USB2.0 HS OTG.................................................................................................................. 5-1
5.2 Key Features of USB2.0 HS OTG ........................................................................................................... 5-1
5.3 Block Diagram of USB2.0 HS OTG ......................................................................................................... 5-2
5.4 Modes of Operation ................................................................................................................................. 5-3
5.4.1 DMA Mode........................................................................................................................................ 5-3
5.4.2 Slave Mode....................................................................................................................................... 5-3
5.5 Power Management Unit Setting ............................................................................................................. 5-4
5.5.1 Normal Mode .................................................................................................................................... 5-4
5.5.2 Stop/Deep Stop/Sleep Mode ............................................................................................................ 5-4
5.6 Register Map............................................................................................................................................ 5-5
5.6.1 Overview of Register Map ................................................................................................................ 5-5
5.6.2 OTG LINK CSR Memory Map .......................................................................................................... 5-6
5.6.3 OTG FIFO Address Mapping............................................................................................................ 5-7
5.6.4 Application Access to the CSRs ....................................................................................................... 5-9
5.7 I/O Description ....................................................................................................................................... 5-10
5.8 Register Description............................................................................................................................... 5-11
5.8.1 Register Map .................................................................................................................................. 5-11
5.8.2 USB PHY Control Registers ........................................................................................................... 5-26
5.8.3 OTG LINK Core Registers (OTG Global Registers)....................................................................... 5-30
5.8.4 Host Mode Registers (Host Global Registers) ............................................................................... 5-53
5.8.5 Host Mode Registers (Host Port Control and Status Registers) .................................................... 5-57
5.8.6 Host Mode Registers (Host Channel-Specific Registers)............................................................... 5-60
5.8.7 Device Mode Registers (Device Global Registers) ........................................................................ 5-65
6 Modem Interface.........................................................................................6-1
6.1 Overview of Modem Interface .................................................................................................................. 6-1
6.2 Key Features of Modem Interface............................................................................................................ 6-2
6.3 Interrupt Ports .......................................................................................................................................... 6-2
6.3.1 Wakeup............................................................................................................................................. 6-2
6.4 Address Mapping ..................................................................................................................................... 6-3
6.5 Timing Diagram........................................................................................................................................ 6-4
6.5.1 Standard Mode Write, Read Timing ................................................................................................. 6-4
6.5.2 Address Muxed Mode Write, Read Timing....................................................................................... 6-6
6.6 I/O Description ......................................................................................................................................... 6-8
6.7 Software Interface and Registers............................................................................................................. 6-8
6.8 Register Description................................................................................................................................. 6-9
6.8.1 Register Map .................................................................................................................................... 6-9
7 SD/MMC Controller.....................................................................................7-1
7.1 Overview of SD/ MMC Controller............................................................................................................. 7-1
7.2 Key Features of SD/ MMC Controller ...................................................................................................... 7-1
7.3 Block Diagram of SD/ MMC Controller .................................................................................................... 7-2
7.4 Operation Sequence ................................................................................................................................ 7-3
7.4.1 SD Card Detection Sequence .......................................................................................................... 7-3
7.4.2 SD Clock Supply Sequence ............................................................................................................. 7-4
7.4.3 SD Clock Stop Sequence ................................................................................................................. 7-5
7.4.4 SD Clock Frequency Change Sequence.......................................................................................... 7-6