True Ide Mdma Mode Timing Diagram - Samsung S5PC110 Manual

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5.7 TRUE IDE MDMA MODE TIMING DIAGRAM

The ATAPI MDMA streams data continuously across the ATA interface between the host and the target device.
This transfer class allows either the driver or host to pause or terminate the data flow. To support various transfer
speed classes, the CPU programs appropriate timing parameters. The ATA_CS0n and CS1n are inactive during
MDMA transfer. The ATA Host controller is always the master in the MDMA transfer classes. The MDMA has
three transfer modes (Mode 0 ~ 2). The fastest mode is mode 2.
The defines the relationships between host and device interface signals for data transfer. The
Figure 5-4
describes the timing parameters of MDMA read and write transfer.
5-2
tm
td
tEOC
td+tEOC
unit: ns
Figure 5-4 MDMA Timing Diagram
Table 5-2 MDMA Timing Parameters
MODE0
(50, --)
(215, --)
(265, --)
(480, --)
5 COMPACT FLASH CONTROLLER
MODE1
(30, --)
(80, --)
(70, --)
(150, --)
Table
MODE2
(25, --)
(70, --)
(50, --)
(120, --)
5-7