Samsung S5PC110 Manual page 635

S5PC110_UM
3.8.3.5 DMA Transfer Size Register (DMA_TRANS_SIZE, R/W, Address = 0xB060_0414)
DMA_TRANS_
SIZE
-
TS
3.8.3.6 DMA Transfer Command Register (DMA_TRANS_CMD, W, Address = 0xB060_0418)
DMA_TRANS_
Bit
CMD
- [31:19]
TDC [18]
- [17]
TEC [16]
- [15:1]
TR [0]
Bit
[31:24] Reserved
[23:0]
Transfer Size
The number of bytes to be transferred to the AHB by the DMA
engine. Transfer size must be less than 16MBytes.
If the DMA source or destination address is in the OneNAND
interface slave address space, TS (Transfer Size) must be the
multiple of 2 because OneNAND interface slave does NOT
support BYTE transactions.
Reserved
Transfer Done Clear
When this bit is set to 1, the TD (Transfer Done) bit flag of the DMA
Transfer Status Register (DMA_TRANS_STATUS) in the DMA
engine is cleared to 0
Reserved
Transfer Error Clear
When this bit is set to 1, the TE (Transfer Error) bit flag of the DMA
Transfer Status Register (DMA_TRANS_STATUS) in the DMA
engine is cleared to 0
Reserved
Transfer Run
When this bit is set to 1, the DMA engine starts to transfer data
from the source memory to the destination memory in the AHB
Description
Description
3 ONENAND CONTROLLER
Initial State
-
000000h
Initial State
-
0b
-
0b
-
0b
3-33