Block Diagram Of S5Pc110 - Samsung S5PC110 Manual

S5PC110_UM

1.2 BLOCK DIAGRAM OF S5PC110

shows the complete block diagram of S5PC110.
Figure 1-1
System Peripheral
RTC
PLL x 4
Timer with PWM (4ch)
Watchdog Timer
DMA (24ch)
Keypad (14x8)
TS- ADC (12bit/10ch)
Connectivity
Audio IF
IIS x 3 / PCM x 3
SPDIF / AC97
Storage IF
HSMMC/ SD x 4
ATA
Connectivity
USB Host 2. 0 / OTG 2.0
UART x 4
IIC x 3
HS- SPI x 2
Modem IF (16KB DPSRAM )
GPIO
CPU Core
CortexA8
32KB/32KB I/ D cache
800MHz/1 GHz @ 1.1V/1.2V
512KB
NEON
L 2 cache
96 KB
RAM
Multi layer AHB / AXI Bus
Crypto
Engines
Power
Management
Clock gating /
Power gating /
Dynamic Voltage
Frequency Scaling
Figure 1-1 S5PC110 Block Diagram
1 OVERVIEW OF S5PC110
12 MP Camera IF / MIPI CSI-2
Codec H. 263/H. 264/ MPEG4
Decoder MPEG2/VC-1/ Divx
3 D Graphics engine
64 KB
ROM
Audio
DSP
Memory Interface
LPDDR1 / OneDRAM
Multimedia
1080p 30 fps MFC
2 D VG /
NTSC / PAL TV out
& HDMI
JPEG Codec
TFT LCD controller
XGA resolution
SRAM / ROM
( Flex) OneNAND
SLC / MLC NAND
with 16 bit ECC
LPDDR2 / DDR2
1-2