Samsung S5PC110 Manual page 689

S5PC110_UM
5.11.1.1 ATA Control Register (ATA_CONTROL, R/W, Address = 0xE820_0000)
ATA_CONTROL
Reserved [31:2]
clk_down_ready
ata_enable
5.11.1.2 ATA Status Register (ATA_STATUS, R, Address = 0xE820_0004)
ATA_STATUS Bit
Reserved [31:6]
atadev_cblid [5]
atadev_irq [4]
atadev_iordy [3]
atadev_dmareq [2]
xfr_state [1:0]
Bit
Reserved
[1] Status for clock down
This bit is asserted in idle state if ATA_CONTROL bit [0]
is zero.
0 = Not ready for clock down
1 = Ready for clock down
[0] Enables ATA
0 = Disables ATA and preparation for clock down.
1 = Enables ATA.
Reserved
ATAPI cable identification
ATAPI interrupt signal line
ATAPI iordy signal line
ATAPI dmareq signal line
Transfer state
2'b00 = Idle state
2'b01 = Transfer state
2'b10 = Abort state
2'b11 = Wait for completion state
Description
Description
5 COMPACT FLASH CONTROLLER
R/W Initial State
R
R
R/W
R/W Initial State
R
R
R
R
R
R
0x0
0x1
0x0
0x0
0x0
0x0
0x1
0x0
0x0
5-17