Samsung S5PC110 Manual page 337

S5PC110_UM
CLK_GATE_IP0
Reserved
CLK_G3D
Reserved
CLK_IMEM
CLK_PDMA1
CLK_PDMA0
CLK_MDMA
CLK_DMC1
CLK_DMC0
Bit
[11:9] Reserved
[8] Gating all clocks for G3D
(0: mask, 1: pass)
[7:6] Reserved
[5] Gating all clocks for IMEM
(0: mask, 1: pass)
[4] Gating all clocks for PDMA1
(0: mask, 1: pass)
[3] Gating all clocks for PDMA0
(0: mask, 1: pass)
[2] Gating all clocks for MDMA
(0: mask, 1: pass)
[1] Gating all clocks for DMC1
(0: mask, 1: pass)
[0] Gating all clocks for DMC0
(0: mask, 1: pass)
Description
3 CLOCK CONTROLLER
Gated Clock Name
PCLK_G2D
Reserved
ACLK_G3D
SCLK_G3D
Reserved
ACLK_IMEM
ACLK_PDMA1
PCLK_PDMA1
ACLK_PDMA0
PCLK_PDMA0
ACLK_MDMA
PCLK_MDMA
ACLK_DMC1
PCLK_DMC1
SCLK_DMC0
ACLK_DMC0
PCLK_DMC0
Initial State
0x7
1
0x3
1
1
1
1
1
1
3-40