Clock Generation - Samsung S5PC110 Manual

S5PC110_UM

3.4 CLOCK GENERATION

shows block diagram of the clock generation logic. An external crystal clock is connected to the
Figure 3-3
oscillation amplifier. The PLL converts low input frequency to high-frequency clock required by S5PC110. The
clock generator block also includes a built-in logic to stabilize the clock frequency after each system reset, since
clock takes time before stabilizing.
also shows two types of clock mux. Clock mux in grey color represents glitch-free clock mux, which is
Figure 3-3
free of glitches if clock selection is changed. Clock mux in white color represents non-glitch-free clock mux, which
can suffer from glitches when changing clock sources. Care must be taken in using each of clock muxes. For
glitch-free mux, it should be guaranteed that both of clock sources are running when clock selection is changed
from one to the other. If that's not the case, clock changing is not finished fully and resulting clock output can have
unknown states. For non-glitch-free clock mux, it is possible to have a glitch when clock selections are changed.
To prevent the glitch signals, it is recommended to disable output of non-glitch-free muxes before trying to change
clock sources. After clock changing is completed, users can re-enable output of the non-glitch-free clock mux so
that there will be no glitches resulting from clock changes. Masking output of non-glitch-free muxes are handled by
clock source control registers.
Clock dividers shown in
decided by clock divider registers on run-time. Some clock dividers can only have one dividing value and user
cannot change them and does not have corresponding fields in clock divider registers.
indicates possible dividing value in parentheses. Those diving values can be
Figure 3-3
3 CLOCK CONTROLLER
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