Samsung S5PC110 Manual page 312

S5PC110_UM
Register
CLK_SRC_MASK1
Reserved
CLK_DIV0
CLK_DIV1
CLK_DIV2
CLK_DIV3
CLK_DIV4
CLK_DIV5
CLK_DIV6
CLK_DIV7
Reserved
CLK_GATE_IP0
CLK_GATE_IP1
CLK_GATE_IP2
CLK_GATE_IP3
CLK_GATE_IP4
Reserved
CLK_GATE_BLOCK
CLK_GATE_IP5
Reserved
CLK_OUT
Reserved
CLK_DIV_STAT0
CLK_DIV_STAT1
Reserved
CLK_MUX_STAT0
CLK_MUX_STAT1
Reserved
SWRESET
Reserved
Address R/W
0xE010_0284 R/W
0xE010_0288~ -
0xE010_02FC
0xE010_0300 R/W
0xE010_0304 R/W
0xE010_0308 R/W
0xE010_030C R/W
0xE010_0310 R/W
0xE010_0314 R/W
0xE010_0318 R/W
0xE010_031C R/W
0xE010_0320~ -
0xE010_045C
0xE010_0460 R/W
0xE010_0464 R/W
0xE010_0468 R/W
0xE010_046C R/W
0xE010_0470 R/W
0xE010_0474~ -
0xE010_047C
0xE010_0480 R/W
0xE010_0484 R/W
0xE010_0488~ -
0xE010_04FC
0xE010_0500 R/W
0xE010_0504~ -
0xE010_0FFC
0xE010_1000 R
0xE010_1004 R
0xE010_1008~ -
0xE010_10FC
0xE010_1100 R
0xE010_1104 R
0xE010_1108~ -
0xE010_1FFC
0xE010_2000 R/W
0xE010_2004~ -
0xE010_2FFC
Description
Clock source mask 1
Reserved
Set clock divider ratio 0 (System Clocks)
Set clock divider ratio 1 (Multimedia)
Set clock divider ratio 2 (Multimedia)
Set clock divider ratio 3 (Multimedia)
Set clock divider ratio 4 (Connectivity)
Set clock divider ratio 5 (Connectivity)
Set clock divider ratio 6 (Audio & Others)
Set clock divider ratio 7 (IEM_IEC)
Reserved
Control IP clock gating
Control IP clock gating
Control IP clock gating
Control IP clock gating
Control IP clock gating
Reserved
Control block clock gating
Control IP clock gating
Reserved
Select clock output
Reserved
Clock divider status (CLK_DIV0~3)
Clock divider status 1 (CLK_DIV4~5)
Reserved
Clock MUX status 0
Clock MUX status 1
Reserved
Generate software reset
Reserved
3 CLOCK CONTROLLER
Reset Value
0xFFFF_FFFF
-
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
-
0xFFFF_FFFF
0xFFFF_FFFF
0xFFFF_FFFF
0xFFFF_FFFF
0xFFFF_FFFF
-
0xFFFF_FFFF
0xFFFF_FFFF
-
0x0000_0000
-
0x0000_0000
0x0000_0000
-
0x1111_1111
0x0001_0000
-
0x0000_0000
-
3-15