Samsung S5PC110 Manual page 519

S5PC110_UM
Register
VIC1PERIPHID3
VIC1PCELLID0
VIC1PCELLID1
VIC1PCELLID2
VIC1PCELLID3
VIC2IRQSTATUS
VIC2FIQSTATUS
VIC2RAWINTR
VIC2INTSELECT
VIC2INTENABLE
VIC2INTENCLEAR
VIC2SOFTINT
VIC2SOFTINTCLEAR
VIC2PROTECTION
VIC2SWPRIORITYMASK
VIC2PRIORITYDAISY
VIC2VECTADDR0
VIC2VECTADDR1
VIC2VECTADDR2
VIC2VECTADDR3
VIC2VECTADDR4
VIC2VECTADDR5
VIC2VECTADDR6
VIC2VECTADDR7
VIC2VECTADDR8
VIC2VECTADDR9
VIC2VECTADDR10
VIC2VECTADDR11
VIC2VECTADDR12
Address R/W
0xF210_0FEC R
0xF210_0FF0 R
0xF210_0FF4 R
0xF210_0FF8 R
0xF210_0FFC R
0xF220_0000 R
0xF220_0004 R
0xF220_0008 R
0xF220_000C R/W
0xF220_0010 R/W
0xF220_0014 W
0xF220_0018 R/W
0xF220_001C W
0xF220_0020 R/W
0xF220_0024 R/W
0xF220_0028 R/W
0xF220_0100 R/W
0xF220_0104 R/W
0xF220_0108 R/W
0xF220_010C R/W
0xF220_0110 R/W
0xF220_0114 R/W
0xF220_0118 R/W
0xF220_011C R/W
0xF220_0120 R/W
0xF220_0124 R/W
0xF220_0128 R/W
0xF220_012C R/W
0xF220_0130 R/W
1 VECTORED INTERRUPT CONTROLLER
Description
Specifies the Peripheral Identification
Register bit 31:24
Specifies the PrimeCell Identification
Register bit 7:0
Specifies the PrimeCell Identification
Register bit 15:9
Specifies the PrimeCell Identification
Register bit 23:16
Specifies the PrimeCell Identification
Register bit 31:24
Specifies the IRQ Status Register
Specifies the FIQ Status Register
Specifies the Raw Interrupt Status
Register
Specifies the Interrupt Select Register
Specifies the Interrupt Enable Register
Specifies the Interrupt Enable Clear
Register
Specifies the Software Interrupt Register
Specifies the Software Interrupt Clear
Register
Specifies the Protection Enable Register
Specifies the Software Priority Mask
Register
Specifies the Vector Priority Register for
Daisy Chain
Specifies the Vector Address 0 Register
Specifies the Vector Address 1 Register
Specifies the Vector Address 2 Register
Specifies the Vector Address 3 Register
Specifies the Vector Address 4 Register
Specifies the Vector Address 5 Register
Specifies the Vector Address 6 Register
Specifies the Vector Address 7 Register
Specifies the Vector Address 8 Register
Specifies the Vector Address 9 Register
Specifies the Vector Address 10 Register
Specifies the Vector Address 11 Register
Specifies the Vector Address 12 Register
Reset Value
0x00
0x0D
0xF0
0x05
0xB1
0x00000000
0x00000000
-
0x00000000
0x00000000
-
0x00000000
-
0x0
0xFFFF
0xF
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
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