Samsung S5PC110 Manual page 324

S5PC110_UM
3.7.3.3 Clock Source Control Registers (CLK_SRC2, R/W, Address = 0xE010_0208)
CLK_SRC2
Reserved
G2D_SEL
Reserved
MFC_SEL
Reserved
G3D_SEL
Bit
[31:10] Reserved
[9:8] Control MUXG2D, which is the source clock of G2D core
(00:SCLKA2M, 01:SCLKMPLL, 10:SCLKEPLL,
11:SCLKVPLL)
[7:6] Reserved
[5:4] Control MUXMFC, which is the source clock of MFC core
(00:SCLKA2M, 01:SCLKMPLL, 10:SCLKEPLL,
11:SCLKVPLL)
[3:2] Reserved
[1:0] Control MUXG3D, which is the source clock of G3D core
(00:SCLKA2M, 01:SCLKMPLL, 10:SCLKEPLL,
11:SCLKVPLL)
Description
3 CLOCK CONTROLLER
Initial State
0x0
0x0
0x0
0x0
0x0
0x0
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