Samsung S5PC110 Manual page 733

S5PC110_UM 1 DMA CONTROLLER
1.3.1.2 DMALD, DMALDP
"Load" instructs the DMAC to perform DMA load using AXI transactions specified by SAR and CCR. For example,
if you define CCR as 32-bit and burst length as 2, the DMALD generates a bus transaction of 32-bit and burst
length 2. DMALDP notifies the peripheral when the data transfer is complete.
1.3.1.3 DMAST, DMASTP
"Store" instructs the DMAC to transfer data from FIFO to a location specified by DAR, using AXI transactions
specified by DAR and CCR. For example, if you define CCR as 32-bit and burst length as 2, the DMAST
generates a bus transaction of 32-bit and burst length 2. DMASTP notifies the peripheral when the data transfer is
complete.
1.3.1.4 DMASTZ
"Store Zero" instructs the DMAC to store zeros using AXI transactions specified by DAR and CCR. For example, if
you define CCR as 32-bit and burst length as 2, the DMASTZ generates a bus transaction of 32-bit and burst
length 2 with zeros at data bus.
1.3.1.5 DMALP, DMALPEND
"DMALP lc0, 4 [code] ~ DMALPEND lc0" loops (iterates) the "[code]" 4 times. There are two loop counters, lc0
and lc1. You can use nested loop by two loop counters.
1.3.1.6 DMAWFP
This is used for peripheral DMA. "Wait for Peripheral" instructs the DMAC to stop the execution of thread until the
specified peripheral signals a DMA request for that DMA channel.
1.3.1.7 DMAFLUSHP
This is used for peripheral DMA. "Flush Peripheral" clears the state in DMA that describes the contents of the
peripheral. It also sends a message to the peripheral to resend its level status. This instruction asserts DMAACK.
If you need DMAACK at a certain point, place this instruction to that point.
1.3.1.8 DMAEND
Instructs a channel to stop.
1-27