Samsung S5PC110 Manual page 306

S5PC110_UM
SCLK
VPLL
SCLK_ HDMIPHY
XXTI
XusbXTI
SCLK _ HDMI 27M
SCLK _ USBPHY 0
SCLK _ USBPHY 1
SCLK _ HDMIPHY
SCLK
M PLL
SCLK
E PLL
SCLK
V PLL
XXTI
XusbXTI
SCLK _ HDMI 27M
SCLK _ USBPHY 0
SCLK _ USBPHY 1
SCLK _ HDMIPHY
SCLK
M PLL
SCLK
E PLL
SCLK
V PLL
XXTI
XusbXTI
SCLK _ HDMI 27M
SCLK _ USBPHY 0
SCLK _ USBPHY 1
SCLK _ HDMIPHY
SCLK
M PLL
SCLK
E PLL
SCLK
V PLL
XXTI
PCMCDCLK 0
SCLK _ HDMI 27M
SCLK _ USBPHY 0
SCLK _ USBPHY 1
SCLK _ HDMIPHY
SCLK
M PLL
SCLK
E PLL
SCLK
V PLL
I2 SCDCLK 1
PCMCDCLK 1
SCLK _ HDMI 27M
SCLK _ USBPHY 0
SCLK _ USBPHY 1
SCLK _ HDMIPHY
SCLK
M PLL
SCLK
E PLL
SCLK
V PLL
I2 SCDCLK 2
PCMCDCLK 2
SCLK _ HDMI 27M
SCLK _ USBPHY 0
SCLK _ USBPHY 1
SCLK _ HDMIPHY
SCLK
M PLL
SCLK
E PLL
SCLK
V PLL
XXTI
XusbXTI
SCLK _ HDMI 27M
SCLK _ USBPHY 0
SCLK _ USBPHY 1
SCLK _ HDMIPHY
SCLK
M PLL
SCLK
E PLL
SCLK
V PLL
MUX
DAC
0
SCLK _ DAC/ TVENC
MUX
1
0
1
0
DIV
TBLK
(1~16)
1
MUX
HDMI
MUX
CAM 0,1
SCLK _ CAM 0, 1 ( PAD)
DIV
CAM0,1
(1~16)
MOUT
CAM 0,1
MUX
FIMD
DIV
FIMD
(1~16)
MOUT
FIMD
MUX
MMC0~3
DIV
MMC 0~3
(1~16)
MOUT
MMC 0 ~3
MUX
AUDIO 0
DIV
AUDIO 0
(1~16)
MOUT
AUDIO 0
MUX
AUDIO 1
DIV
AUDIO 1
(1~16)
MOUT
AUDIO 1
MUX
AUDIO 2
DIV
AUDIO 2
(1~16)
MOUT
AUDIO 2
MUX
FIMC _ LCLK
DIV
SCLK_ FIMC_ LCLK
FIMC_LCLK
(1~16)
MOUT
FIMC _ LCLK
Figure 3-3
SCLK
A 2 M
SCLK
MPLL
SCLK
E PLL
SCLK
V PLL
SCLK
A2 M
SCLK
MPLL
SCLK
MIXER
E PLL
SCLK _ MIXER
SCLK
V PLL
SCLK
SCLK _ HDMI A 2 M
SCLK
MPLL
SCLK
E PLL
SCLK
V PLL
SCLK _ PIXEL
XXTI
XusbXTI
SCLK _ HDMI 27 M
SCLK _ USBPHY 0
SCLK _ USBPHY 1
SCLK _ HDMIPHY
SCLK
M PLL
SCLK
E PLL
SCLK
V PLL
XXTI
XusbXTI
SCLK _ HDMI 27 M
SCLK_ FIMD
SCLK _ USBPHY 0
SCLK _ USBPHY 1
SCLK _ HDMIPHY
SCLK
M PLL
SCLK
E PLL
SCLK
V PLL
XXTI
XusbXTI
SCLK _ HDMI 27 M
SCLK _ MMC 0 ~ 3
SCLK _ USBPHY 0
SCLK _ USBPHY 1
SCLK _ HDMIPHY
SCLK
M PLL
SCLK
E PLL
SCLK
V PLL
XXTI
XusbXTI
SCLK _ HDMI 27 M
SCLK _ AUDIO0
SCLK _ USBPHY 0
SCLK _ USBPHY 1
SCLK _ HDMIPHY
SCLK
M PLL
SCLK
E PLL
SCLK
V PLL
XXTI
XusbXTI
SCLK _ HDMI 27 M
SCLK _ AUDIO1
SCLK _ USBPHY 0
SCLK _ USBPHY 1
SCLK _ HDMIPHY
SCLK
M PLL
SCLK
E PLL
SCLK
V PLL
SCLK _ AUDIO2
S5PC110 Clock Generation Circuit 1
3 CLOCK CONTROLLER
MUX
MFC
DIV
(1~16)
MOUT
MFC
MUX
G 3 D
DIV
(1~16)
MOUT
G 3 D
MUX
G2 D
DIV
(1~16)
MOUT
G 2 D
MUX
CSIS
DIV
(1~16)
MOUT
CSIS
MUX
SPI0~2
DIV
(1~16)
MOUT
SPI 0 ~ 2
MUX
PWI
DIV
(1~16)
MOUT
PWI
MUX
UART 0 ~3
DIV
(1~16)
MOUT
UART 0 ~3
MUX
PWM
DIV
(1~16)
MOUT
PWM
SCLK _ AUDIO 0
SCLK _ AUDIO 1
SCLK _ AUDIO 2
SCLK _ MFC
MFC
SCLK _G 3D
G3 D
SCLK _G2 D
G2 D
SCLK _ CSIS
CSIS
SCLK _SPI0~ 2
SPI0~2
SCLK _ PWI
PWI
SCLK _ UART0 ~ 3
UART 0~3
SCLK _ PWM
PWM
MUX
SPDIF
SCLK _ SPDIF
3-9