Samsung S5PC110 Manual page 694

S5PC110_UM
5.11.2.5 ATA Multi_word DMA Timing (ATA_MDMA_TIME, R/W, Address = 0xE820_0028)
ATA_MDMA_TIME
Reserved
dma_teoc
dma_t2
dma_t1
5.11.2.6 ATA PIO Time (ATA_PIO_TIME, R/W, Address = 0xE820_002C)
ATA_PIO_TIME
Reserved
pio_teoc
pio_t2
pio_t1
5.11.2.7 ATA UDMA Time (ATA_UDMA_TIME, R/W, Address = 0xE820_0030)
ATA_UDMA_TIME
Reserved
udma_tdvh
udma_tdvs
udma_trp
udma_tss
udma_tackenv
Bit
[31:20] Reserved
[19:12] DMA timing parameter, Teoc, end of cycle time
[11:4] DMA timing parameter, tD, DIOR/DIOWn pulse width
[3:0] DMA timing parameter, tM, CS0,1n valid to DIOR/Wn
Bit
[31:20] Reserved
[19:12] PIO timing parameter, teoc, end of cycle time
It shall not have zero value.
[11:4] PIO timing parameter, t2, DIOR/Wn pulse width
It cannot have zero value.
[3:0] PIO timing parameter, t1, address valid to DIOR/Wn
Bit
[31:28] Reserved
[27:24] UDMA timing parameter tDVH
[23:16] UDMA timing parameter tDVS
It cannot have zero value.
[15:8] UDMA timing parameter tRP
[7:4] UDMA timing parameter, tSS
[3:0] UDMA timing parameter tENV (envelope time (From
DMACKn to STOP and HDMARDYn), tACK (setup and
hold time for DMACKn)
Description
Description
Description
5 COMPACT FLASH CONTROLLER
R/W Initial State
R
R/W
R/W
R/W
R/W Initial State
R
R/W
R/W
R/W
R/W Initial State
R
R/W
R/W
R/W
R/W
R/W
0x0
0x2C
0x23
0x8
0x0
0x27
0x2f
0xa
0x0
0x8
0x0b
0x1a
0x8
0x3
5-22