Samsung S5PC110 Manual page 628

S5PC110_UM
3.8.2.2 OneNAND Interface Command Register (ONENAND_IF_CMD, W, Address = 0xB060_0104)
ONENAND_
IF_CMD
- [31:18]
INTC [17:16]
- [15:2]
WR
-
Bit
Reserved
OneNAND INT Done Clear
When this bit is set to 1, the INTD (OneNAND INT done) bit flag
of the OneNAND Interface Status Register
(ONENAND_IF_STATUS) is cleared to 0.
INTC[0]
1b = Device[0] OneNAND Interrupt Done clear
0b = no operation
INTC[1]
1b = Device[1] OneNAND Interrupt Done clear
0b = no operation
Reserved
[1]
Warm Reset
For OneNAND warm reset, writing 1 to this bit makes nRP pin of
OneNAND device low during 20 CLK. It is mandatory to assert
the nRP pin to zero for warm reset during tRP time and the tRP
time is more than 200ns.
After warm reset, it should wait for tREADY1 to access the
OneNAND BootRAM and tREADY2 time is needed to issue the
new command. tREADY1 time and tREADY2 time are at least
5us and 500us respectively.
1b = nPR pin low for 20 CLK
0b = no operation
[0] Reserved
Description
3 ONENAND CONTROLLER
Initial State
-
00h
-
0b
-
3-26