Samsung S5PC110 Manual page 583

S5PC110_UM
1.4.1.12 AC Timing Register for the Data of memory (TimingData, R/W, Address = 0xF000_0038,
0xF140_0038)
TIMINGDATA
t_wtr [31:28]
t_wr [27:24]
t_rtp [23:20]
cl [19:16]
Reserved [15:12]
wl [11:8]
Reserved
rl
NOTE: * tDAL (Auto precharge write recovery + precharge time) = t_wr + t_rp (automatically calculated)
Bit
Internal write to Read command delay, in cycles
t_wtr * T(mclk) should be greater than or equal to the minimum
value of memory tWTR.
t_wtr must be 0x1 in case of JEDEC LPDDR.
Write recovery time, in cycles
t_wr * T(mclk) should be greater than or equal to the minimum
value of memory tWR
Internal read to Precharge command delay, in cycles
t_rtp * T(mclk) should be greater than or equal to the minimum
value of memory tRTP.
t_rtp must be 0x1 in case of JEDEC LPDDR.
CAS Latency (for LPDDR/DDR/DDR2), in cycles
cl should be greater than or equal to the minimum value of
memory CL.
Should be zero
Write data latency (for only LPDDR2), in cycles
wl should be greater than or equal to the minimum value of
memory WL
[7:4] Should be zero
[3:0] Read data latency (for only LPDDR2), in cycles
rl should be greater than or equal to the minimum value of
memory RL
Description
1 DRAM CONTROLLER
Initial
R/W
State
R/W 0x1
R/W 0x2
R/W 0x1
R/W 0x3
0x0
R/W 0x2
0x0
R/W 0x4
1-40