Bus Configuration Register (Buspri0, Buspri1, And Busmisc) - Samsung S3C2416 User Manual

SYSTEM CONTROLLER
8.7

BUS CONFIGURATION REGISTER (BUSPRI0, BUSPRI1, AND BUSMISC)

To improve AHB bus performance, software must control the arbitration scheme and type.
Register
BUSPRI0 0x4C00_0050
S3C2416 consists of 2 hierarchical AHB buses. The arbitration priority and order can be configured with BUSPRI0
registers. You can see specific priority number that assigned to each AMBA master in User's Manual section '04-
BUS PRIORITIES'. The number of masters of AHB-S and AHB-I bus is 16 and 9 respectively.
Each TYPE field of BUSPRI0 register has three possible choices as follows:
1. 2'b00: the fixed type
2. 2'b01: the last granted maser has the lowest priority
3. 2'b10: the rotated type
4. 2'b11: undefined
BUSPRI0 Bit
RESERVED [31:16]
TYPE_S [15:14]
RESERVED [13:12]
[11:8]
ORDER_S
TYPE_I [7:6]
RESERVED [5:3]
2-36
Address R/W
R/W
-
Priority type for AHB-System bus
-
Fixed priority order for AHB-S bus
Value
4'h0 0-1-2-3-4-5-6-7-8-9-10-
11-12-13-14-15
4'h1 1-2-3-4-5-6-7-8-9-10-11-
12-13-14-15-0
4'h2 2-3-4-5-6-7-8-9-10-11-12-
13-14-15-0-1
4'h3 3-4-5-6-7-8-9-10-11-12-0-
4'h4 4-5-6-7-8-9-10-11-12-13-
14-15-0-1-2-3
4'h5 5-6-7-8-9-10-11-12-13-14-
15-0-1-2-3-4
4'h6 6-7-8-9-10-11-12-13-14-
15-0-1-2-3-4-5
4'h7 7-8-9-10-11-12-13-14-15-
0-1-2-3-4-5-6
Priority type for AHB-Image bus
-
Description
Bus priority control register 0
Description
Priority Value
4'h8
4'h9
4'ha
4'hb
1-2
4'hc
4'hd
4'he
4'hf
S3C2416X RISC MICROPROCESSOR
Priority
8-9-10-11-12-13-14-15-0-
1-2-3-4-5-6-7
9-10-11-12-13-14-15-0-1-
2-3-4-5-6-7-8
10-11-12-13-14-15-0-1-2-
3-4-5-6-7-8-9
11-12-13-14-15-0-1-2-3-
4-5-6-7-8-9-10
12-13-14-15-0-1-2-3-4-5-
6-7-8-9-10-11
13-14-15-0-1-2-3-4-5-6-
7-8-9-10-11-12
14-15-0-1-2-3-4-5-6-7-8-
9-10-11-12-13
15-0-1-2-3-4-5-6-7-8-9-
10-11-12-13-14
Reset Value
0x0000_0000
Initial
Value
0x0000
0x0
0x0
0x0
0x0
0x0