Functional Description Of Watchdog Timer; Watchdog Timer Operation; Wtdat And Wtcnt; Wdt Start - Samsung S5PC110 Manual

S5PC110_UM

3.3 FUNCTIONAL DESCRIPTION OF WATCHDOG TIMER

3.3.1 WATCHDOG TIMER OPERATION

shows the functional block diagram of the watchdog timer. The watchdog timer uses PCLK as its
Figure 3-1
source clock. The PCLK frequency is prescaled to generate the corresponding watchdog timer clock, and the
resulting frequency is divided again.
PCLK 8-bit Prescaler
WTCON[15:8]
The prescaler value and frequency division factor are specified in the watchdog timer control (WTCON) register.
Valid prescaler values range from 0 to 2
Use the following equation to calculate the watchdog timer clock frequency and the duration of each timer clock
cycle:
− t_watchdog = 1/( PCLK / (Prescaler value + 1) / Division_factor )

3.3.2 WTDAT AND WTCNT

Once the watchdog timer is enabled, the value of watchdog timer data (WTDAT) register cannot be automatically
reloaded into the timer counter (WTCNT). Therefore, an initial value must be written to the watchdog timer count
(WTCNT) register, before the watchdog timer starts.

3.3.3 WDT START

To start WDT, set WTCON[0] and WTCON[5] as 1.
MUX
1/16
1/32
(Down Counter)
1/64
1/128
WTCON[4:3]
Figure 3-1 Watchdog Timer Block Diagram
8
-1. The frequency division factor can be selected as, 16, 32, 64, or 128.
WTDAT
Interrupt
WTCNT
Reset Signal Generator
WTCON[2] WTCON[0]
3 WATCHDOG TIMER
RESET
3-2