Samsung S5PC110 Manual page 830

S5PC110_UM
It is recommended to select UDIVSLOTn as described in the following table:
Num of 1's
0 0x0000(0000_0000_0000_0000b)
1 0x0080(0000_0000_0000_1000b)
2 0x0808(0000_1000_0000_1000b)
3 0x0888(0000_1000_1000_1000b)
4 0x2222(0010_0010_0010_0010b)
5 0x4924(0100_1001_0010_0100b)
6 0x4A52(0100_1010_0101_0010b)
7 0x54AA(0101_0100_1010_1010b)
2. Baud Rate Error Tolerance
UART Frame error should be less than 1.87%(3/160)
tUPCLK = (UBRDIVn + 1) x 16 x 1Frame / (PCLK or SCLK_UART)
tEXTUARTCLK = 1Frame / baud-rate
UART error = (tUPCLK − tEXTUARTCLK) / tEXTUARTCLK x 100%
1Frame = start bit + data bit + parity bit + stop bit.
3. UART Clock and PCLK Relation
There is a constraint on the ratio of clock frequencies for PCLK to UARTCLK.
The frequency of UARTCLK must be no more than 5.5/3 times faster than the frequency of PCLK:
FUARTCLK <= 5.5/3 X FPCLK
This allows sufficient time to write the received data to the receive FIFO
1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER
UDIVSLOTn Num of 1's
8 0x5555(0101_0101_0101_0101b)
9 0xD555(1101_0101_0101_0101b)
10 0xD5D5(1101_0101_1101_0101b)
11 0xDDD5(1101_1101_1101_0101b)
12 0xDDDD(1101_1101_1101_1101b)
13 0xDFDD(1101_1111_1101_1101b)
14 0xDFDF(1101_1111_1101_1111b)
15 0xFFDF(1111_1111_1101_1111b)
tUPCLK: Real UART Clock
tEXTUARTCLK: Ideal UART Clock
FUARTCLK = baudrate x 16
UDIVSLOTn
1-28