Samsung S5PC110 Manual page 558

S5PC110_UM
is for DDR2 having an internal DLL. An internal DLL exists which allows it to send the data after an
Figure 1-6
exact amount of read latency. If we assume there are minimal or no board/ PHY input delay, if sampling the
negedge (Q1, Q3 sampling), since the data gets saved into the PHY read data input FIFO, the controller sends
the read data to the AXI read channel in 'read latency + 1(read fetch)' cycles. The read fetch cycle is set using the
ConControl.rd_fetch bit-field.
Figure 1-7
is different from
Figure 1-7
one cycle slower than T4/T5 shown in
sampled read data is saved slowly into the read input FIFO.
Timing Diagram of Read Data Capture (DDR2, non-zero delay, RL=3, rd_fetch=2)
because a delay exists. Negedge sampling happens at T5 and T6, which is
Figure 1-6
1-4. Therefore, the read fetch cycle should be set to two since the
Figure
1 DRAM CONTROLLER
1-15