Samsung S5PC110 Manual page 358

S5PC110_UM
3.7.10.11 IEM Control SFRs
•
APLL_CON0_L8, R/W, Address = 0xE010_3100
•
APLL_CON0_L7, R/W, Address = 0xE010_3104
•
APLL_CON0_L6, R/W, Address = 0xE010_3108
•
APLL_CON0_L5, R/W, Address = 0xE010_310C
•
APLL_CON0_L4, R/W, Address = 0xE010_3110
•
APLL_CON0_L3, R/W, Address = 0xE010_3114
•
APLL_CON0_L2, R/W, Address = 0xE010_3118
•
APLL_CON0_L1, R/W, Address = 0xE010_311C
•
APLL_CON1_L8, R/W, Address = 0xE010_3300
•
APLL_CON1_L7, R/W, Address = 0xE010_3304
•
APLL_CON1_L6, R/W, Address = 0xE010_3308
•
APLL_CON1_L5, R/W, Address = 0xE010_330C
•
APLL_CON1_L4, R/W, Address = 0xE010_3310
•
APLL_CON1_L3, R/W, Address = 0xE010_3314
•
APLL_CON1_L2, R/W, Address = 0xE010_3318
•
APLL_CON1_L1, R/W, Address = 0xE010_331C
APLL_CON0_L1 ~ 8
Reserved
MDIV
Reserved
PDIV
Reserved
SDIV
Each register of APLL_CON0_L1 ~ 7 configures P/M/S/VCO_FREQ values for ARM PLL at IEM performance
level-1 to 8.
APLL_CON1_L1 ~ 8
AFC_ENB
Reserved
AFC
Bit
[31:26] Reserved
[25:16] APLL M divide value
[15:14] Reserved
[13:8] APLL P divide value
[7:3] Reserved
[2:0] APLL S divide value
Bit
[31] Decides whether AFC is enabled or not. Active low.
AFC selects adaptive frequency curve of VCO for wide
range, high phase noise (or jitter) and fast lock time.
(LOW: AFC is enabled, HIGH: AFC is disabled)
[30:5] Reserved
[4:0] AFC value
Description
Description
3 CLOCK CONTROLLER
Initial State
0x00
0x0C8
0
0x3
0
0x1
Initial State
0x0
0x0
0x0
3-61