Samsung S5PC110 Manual page 772

Risc microprocessor
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S5PC110_UM
2.8.1.5 TICK Fractional Counter Register (TFCNTB, R/W, Address = E260_0010)
TFCNTB
Reserved
Tick Fractional Count
Buffer
2.8.1.6 Interrupt Counter Register (ICNTB, R/W, Address = E260_0018)
Real Interrupt Counter Value = ICNTB+1.
If ICNTB value is 0, interrupt occurs at every TICK.
ICNTB
Interrupt Manual Update
Interrupt Count Buffer
2.8.1.7 Interrupt Observation Register (ICNTO, R, Address = E260_001C)
ICNTO
Reserved
Interrupt Count
Observation
Bit
[31:16]
Reserved
[15:0]
Tick Fractional Count Buffer Register
Bit
[31]
0 = No operation
1 = Update ICNTB
This bit is auto-cleared.
[30:0]
Interrupt Count Buffer Register
Bit
[31]
Reserved
[30:0]
Interrupt Count Observation Register
Description
Description
Description
2 SYSTEM TIMER
Initial State
0x0
0x0
Initial State
0x0
0x0
Initial State
0x0
0x0
2-12

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