S5PC110_UM
5.8.4.4 Host Periodic Transmit FIFO/QUEUE Status Register (HPTXSTS, R, Address = 0xEC00_0410)
This read-only register contains the free space information for the Periodic TxFIFO and the Periodic Transmit
Request Queue.
HPTXSTS
Bit
PTxQTop
[31:24]
PTxQSpcAvail
[23:16]
PTxFSpcAvail
[15:0]
Top of the Periodic Transmit Request Queue
This indicates the entry in the Periodic Tx Request Queue
that is currently being processes by the MAC.
This register is used for debugging.
Bit [31]: Odd/Even (micro)frame
•
- 1'b0: send in even (micro)frame
- 1'b1: send in odd (micro)frame
Bits [30:27]: Channel/endpoint number
•
Bits [26:25]: Type
•
-2'b00: IN/OUT
-2'b01: Zero-length packet
-2'b10: CSPLIT
-2'b11: Disable channel command
Bit[24]: Terminate
•
Periodic Transmit Request Queue Space Available
Indicates the number of free locations available to be written
in the Periodic Transmit Request Queue. This queue holds
both IN and OUT requests.
8'h0: Periodic Transmit Request Queue is full
•
8'h1: 1 location available
•
8'h2: 2 location available
•
n: n locations available (0 ≤ n ≤ 8)
•
Others: Reserved
•
Periodic Transmit Data FIFO Space Available
Indicates the number of free locations available to be written
to in the Periodic TxFIFO.
Values are in terms of 32-bit words
16'h0: Periodic TxFIFO is full
•
16'h1: 1 word available
•
16'h2: 2 words available
•
n: n words available (0 ≤ n ≤ 8)
•
Others: Reserved
•
Description
5 USB2.0 HS OTG
R/W
Initial State
R
8'h0
R
8'h8
R
16'h0300
5-55