Samsung S5PC110 Manual page 559

S5PC110_UM 1 DRAM CONTROLLER
To calculate the DDR2 rd_fetch value:
rd_fetch DDR2) = INT((Delay + 0.5T + 0.25T)/T) = INT(Delay/T + 0.75),
Delay: board delay + PHY input/output delay, T: clock period, INT(x): the rounded-up integer value of x
Therefore, rd_fetch must have minimum one value.
Figure 1-8 Timing Diagram of Read Data Capture
(LPDDR/LPDDR2, zero delay, RL=3, rd_fetch=1)
An LPDDR/LPDDR2 does not have an internal DLL. Without an internal DLL as shown in the data is
Figure 1-8
sent out after tDQSCK before the read latency is over. Even if we assume zero delay, since tDQSCK becomes
relatively large in high frequencies, the read fetch cycle should be set to one.
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