Samsung S5PC110 Manual page 727

S5PC110_UM
1.2.1.7 Configuration Register4 for DMA_PERI(0,1) (CR4, R)
• CR4 for DMA_PERI0, R, Address = 0xE090_0E10
• CR4 for DMA_PERI1, R, Address = 0xE0A0_0E10
CR4
PNS
1.2.1.8 Configuration Register DN for DMA_PERI(0,1) (CRdn, R)
• CRDn for DMA_PERI0, R, Address = 0xE090_0E14
• CRDn for DMA_PERI1, R, Address = 0xE0A0_0E14
CRDn
data_buffer_dep
rd_q_dep
rd_cap
wr_q_dep
wr_cap
data_width
Bit
[31:0] Specifies the security state of peripheral request interfaces.
Bit [N] = 1: Assigns peripheral request interface N to non-
secure state.
32'hffff_ffff
Bit
[29:20] Specifies the number of lines that data buffer contains.
b000000111 = 8 lines
[19:16] Specifies the depth of read queue.
b0111 = 8 lines
[14:12] Specifies the read issuing capability that programs the number
of outstanding read transactions.
b011 = 4
[11:8] Specifies the depth of write queue.
b0111 = 8 lines
[6:4] Specifies the write issuing capability that programs the number
of outstanding write transactions.
b011 = 4
[2:0] Specifies the data bus width of AXI interface.
b010 = 32-bit
Description
Description
1 DMA CONTROLLER
Initial State
0xFFFF_FFFF
Initial State
0x7
0x7
0x3
0x7
0x3
0x2
1-21