Mipi D-Phy; Pll - Samsung S5PC110 Manual

Risc microprocessor
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S5PC110_UM

4.7.3 MIPI D-PHY

MIPI D-PHY has three power modes, namely, Run, LP, and ULPS mode
In Run mode, MIPI D-PHY sends and receives data normally.
In LP and ULPS mode, all power MIPI D-PHY is off internally.
In NORMAL mode, all three power modes can be used.
If you want to use MIPI D-PHY, then you should set it in the Run mode. Otherwise, it can enter into LP or ULPS
mode to save static power by setting register in MIPI link.
In IDLE mode, and DEEP-IDLE mode where TOP block is "ON", MIPI D-PHY keeps its operation or power state in
NORMAL.
Before entry to DEEP-IDLE mode where TOP block is "OFF", STOP, and DEEP-STOP mode, it is recommended
that MIPI D-PHY enter into LP or ULPS mode. Before entry to SLEEP, it is recommended that MIPI D-PHY enter
into ULPS mode. For more details about LP and ULPS mode, refer to MIPI D-PHY user's manual.

4.7.4 PLL

PLL has two power modes, namely, Run and Power-down mode
In Run mode, PLL sends and receives data normally. (Iop = max. 2mA@4502A, max. 1mA@4500B)
In Power-down mode, all power to PLL is "OFF" internally. (Ipd = max 80uA)
In NORMAL mode, both power modes can be used.
If you want to use PLL, then you should set it in the Run mode. Otherwise, it can enter into Power-down mode to
save static power by setting register (APLLCON, MPLLCON, EPLLCON, VPLLCON) in SYSCON.
In IDLE mode, and DEEP-IDLE mode where TOP block is "ON", PLL keeps its operation or power state in
NORMAL.
In DEEP-IDLE mode where TOP block is "OFF", APLL, MPLL, and VPLL are powered down automatically by
SYSCON. Note that EPLL is still powered on in this mode to provide proper operating clock to Audio sub-block. In
STOP and SLEEP mode, all PLLs are powered down automatically by SYSCON.
4 POWER MANAGEMENT
4-28

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