Samsung S5PC110 Manual page 789

S5PC110_UM
4.10.1.2 Real Time Clock Control Register (RTCCON, R/W, Address = 0xE280_0040)
The RTCCON register consists of 10 bits such as the RTCEN, which controls the read/ write enable of the BCD
SEL, CNTSEL, CLKRST, TICCKSEL and TICEN for testing, and CLKOUTEN for RTC clock output control.
RTCEN bit controls all interfaces between the CPU and the RTC, therefore it should be set to 1 in an RTC control
routine to enable data read/ write after a system reset. To prevent inadvertent writing into BCD counter registers
the RTCEN bit should be cleared to 0 before power off.
CLKRST is counter reset for 2
RTC operation.
RTCCON Bit
Reserved [31:10]
CLKOUTEN [9]
TICEN [8]
TICCKSEL [7:4]
CLKRST [3]
CNTSEL [2]
CLKSEL [1]
RTCEN [0]
15
clock divider. Before RTC clock setting, 2
Reserved
Enables RTC clock output on XRTCCLKO pad.
0 = Disables
1 = Enables
Enables Tick timer
0 = Disables
1 = Enables
Tick timer sub clock selection.
4'b0000 = 32768 Hz
4'b0010 = 8192 Hz
4'b0100 = 2048 Hz
4'b0110 =512 Hz
4'b1000 =128 Hz
4'b1010 =32 Hz
4'b1100 =8 Hz
4'b1110 =2 Hz
RTC clock count reset.
15
0 = RTC counter (2 clock divider) enable
1 = RTC counter reset and disable
Note: When RTCEN is enabled, CLKRST affects RTC.
BCD count select.
0 = Merge BCD counters
1 = Reserved (Separate BCD counters)
Note: When RTCEN is enabled, CNTSEL affects RTC.
BCD clock select.
15
0 = XTAL 1/2 divided clock
1 = Reserved (XTAL clock only for test)
Note: When RTCEN is enabled, CLKSEL affects RTC.
Enables RTC control.
0 = Disables
1 = Enables
Note: When RTCEN is enabled, you can change the BCD time count
15
setting, 2 clock divider reset, BCD counter select, and BCD clock
select can be performed.
15
clock divider must be reset for exact
Description
4'b0001 = 16384 Hz
4'b0011 = 4096 Hz
4'b0101 =1024 Hz
4'b0111 =256 Hz
4'b1001 =64 Hz
4'b1011 =16 Hz
4'b1101 =4 Hz
4'b1111 =1 Hz
4 REAL TIME CLOCK (RTC)
Initial State
0
0
0
4'b0000
0
0
0
0
4-10